This invention relates to a pattern generator for generating at high speed a large number of patterns, each composed of a plurality of bits, for testing the operation of a semiconductor element, such as, for example, a microprocessor semiconductor integrated circuit, a semiconductor memory or the like.
In a conventional pattern generator of this kind, for example, a memory having stored therein many patterns is read by an electronic computer and the read-out patterns are supplied to a semiconductor element under test. In the prior art, one or more memories of the same operating speed are employed for storing patterns and the stored patterns are successively read out programatically. The more complicated the semiconductor element under test becomes, the more patterns are required and the longer the time of test becomes; therefore, it is desired to test the semiconductor element at as high speed as possible. But a large-capacity memory of high operating speed is not available, so that in order to generate a large number of patterns at high speed, it is necessary to use a large number of small-capacity and expensive high-speed memories, but this presents problems of package and cost.
There has been proposed a system in which a plurality of low-speed memories are simultaneously accessed to read out thereof patterns and the patterns thus read out of the memories are successively derived by a multiplexer and applied to an element under test at high speed. This system does not pose any problem in the case of reading memories in the order of address but, in the case of reading the memories while changing the address at random, for example, skipping over some addresses, a dummy cycle, that is, a cycle in which no pattern is generated, is inserted, so that a semiconductor element is tested at a lower speed than its operating speed and its state may in some cases vary during the dummy cycle. Consequently, no accurate test is achieved, or the test is conducted at a low speed as a whole to result in the test becoming time-consuming. In an actual test, an address for the memory having stored therein patterns is not simply updated but, in many cases, the address changes in a complicated manner, for example, turns back, skips forward or repeatedly circles, by which an accurate test is conducted. Accordingly, it is difficult to simultaneously access the low-speed memories for generating complicated patterns at high speed as a whole.
An object of this invention is to provide a pattern generator in which a large number of complicated patterns can be generated by the combined use of low-speed and high-speed memories at high speed without any dummy cycle to ensure that a complicated semiconductor element is tested in a short time and with high accuracy.